1. Field of the Invention
The present invention relates to the field of computers. More specifically, the present invention relates to computer architecture.
2. Description of the Related Art
A pipelined superscalar processor may fetch and execute instructions speculatively until an actual target address for change of control instructions (i.e., those instructions that modify the program counter from a predetermined increment) can be determined. For example, speculative execution of instructions occurs while waiting for a branch target address to be resolved. The actual target of the branch may not be determined until many instruction cycles after making the branch prediction and speculative fetch of instructions. Meanwhile, speculatively fetched and/or executed instructions and/or TRAP instructions may include changes in program flow.
A pipelined superscalar processor may include a return address stack (RAS), i.e., a stack of return addresses for function, subroutine, or procedure calls. In general, the RAS is accessed using a stack pointer containing the address of the top of the stack. Call instructions push addresses onto the RAS and the RAS pointer is updated accordingly. Return instructions pop addresses from the top of the RAS and the RAS pointer is updated accordingly. A balanced sequence of pushes and pops will ensure correct return addresses. Updates to the RAS pointer and/or the RAS inconsistent with actual program execution may result in misalignment of the RAS pointer to the RAS (i.e., the RAS pointer incorrectly points to a particular entry of the RAS) and/or corruption of RAS content. Such corruption of the RAS content and/or the RAS pointer may occur as a result of mispredicted speculative operations. In addition to mispredicted speculative operations, the RAS pointer and/or RAS content may be corrupted by changes in program flow resulting from program exception handling. Such corruption to the RAS pointer and/or RAS content can impact performance significantly.